1. Field of the Invention
The present invention relates to a semiconductor memory device, and, more particularly, to the improvement on the method of isolating memory cell transistors used in a non-volatile semiconductor memory device, such as EPROM or EEPROM or flash EEPROM.
2. Description of the Related Art
FIG. 1 is a plan view of the typical pattern of the memory cell matrix of an EPROM, FIG. 2A is a cross-sectional view taken along line 2A--2A in FIG. 1, and FIG. 2B is a cross-sectional view taken along line 2B--2B in FIG. 1.
As shown in FIGS. 1 through 2B, a plurality of memory cell transistors are formed in a matrix form in a P-type silicon substrate 1. The broken-line block A in FIG. 1 indicates the area of a single memory cell transistor. Each memory cell transistor comprises a first gate oxide film 2 formed on the substrate 1, a floating gate 3 formed on this first gate oxide film 2, a control gate 5 formed on the floating gate 3 via a second gate insulating film 4 (which is generally called "interpoly insulating film"), an N-type drain diffusion layer 6 and an N-type source diffusion layer 7. The drain diffusion layer 6 is shared by the adjoining memory cell transistors in the same column, while the source diffusion layer 7 is shared by the memory cell transistors in the associated row and those in one adjoining row. Any adjoining memory cell transistors in the same row are isolated by an LOCOS oxide film 8 formed on the substrate 1 by local oxidation. The portion denoted by reference numeral "9" is a contact region for the drain diffusion layer 7 and a bit line BL.
Due to today's demand for a large capacity of a semiconductor memory device, it is desirable that the integration of memory cell transistors be improved. As one way of achieving higher integration, the LOCOS oxide film 8, i.e., the area of the device isolation region, is reduced.
It is however known that bird's beaks are apt to be produced in the LOCOS oxide film, making it difficult to efficiently reduce the area of this oxide film. In particularly, it is difficult to reduce the isolation width X between devices. The bird's beak may adversely affect the reliability of the gate oxide film or the like of the memory cell transistor.
To overcome the problem that the isolation width cannot be made narrower, there has been an attempt to form a groove or trench in the silicon substrate to isolate devices, as disclosed in IEDM Technical Digest, 1989, p. 583 to p. 586, by Yoshiaki Hisamune et al.
The structure of this known trench isolation type memory cell transistor will achieve the purpose of making the isolation width of the device narrower than the structure of isolating devices by the LOCOS oxide film.
As the trench isolation is provided along the channel region of the memory cell transistors, however, a leak current is undesirably produced along the side surface of the trench from the channel region. Further, since stress is applied directly to the channel region in the etching step for providing the trench isolation and the step of burying the insulating film in the trench, the adverse influence on the reliability of the gate oxide film or the like of a cell should also be considered. In addition to the stress, the channel region is exposed so that the channel region and the gate oxide film may be contaminated by a harmful impurity.